Gaya APA

READLER, B, C. (2011). VERILOG BY EXAMPLE: A CONCISE INTRODUSTION FOR FPGA DESIGN . USA: FULL ARC PRESS.

Gaya MLA

READLER, BLAINE, C.. "VERILOG BY EXAMPLE: A CONCISE INTRODUSTION FOR FPGA DESIGN". USA: FULL ARC PRESS, 2011. Text.